This invention relates generally to divider circuits and more particularly to an ultra high speed CMOS divide by 4/5 prescaler circuit. Prescaler circuits for use in high speed dividers, frequency synthesizers, and the like, are well known in the art. A dual-modulas prescaler is a counter whose division ratio can be switched from one value to another by an external control signal. That is, a prescaler can divide by a first factor when an applied control signal is high, or by a second factor when the applied control signal is low. An indepth discussion of prescalers can be found in "Phase-Locked Loops" by Dr. Ronald E. Best, copyright 1984, McGraw-Hill Inc.
In an article entitled "A 250 MHz Dynamic CMOS Dual Modulas (.div.8/9) Prescaler" by Chris Groves et al. and beginning on page 110 of the minutes of the 1984 Conference on Advance Research in VLSI, MIT, there is described a dual modulas (.div.8/9) prescaler for use in a digital 250 MHz CMOS programmable divider circuit. This prescaler comprises three cascaded standard CMOS inverters, one NOR gate, and three functionally distinct inverter circuits. Unfortunately, the circuit operates in a primarily sequential manner thus limiting its speed. Furthermore, the use of a significant number of components further restricts speed and increases the circuits power consumption.